It is well known in the electronic arts that electrostatic discharge (ESD) can damage and/or destroy semiconductor devices. Protection circuitry is generally designed into semiconductor devices to reduce the risk of damage due to ESD. For example, thyristors are often used to reduce damage that can occur as a result of an ESD event on an input-output (I/O) of a semiconductor device. A circuit representation of a thyristor used as an I/O protection circuit is illustrated in FIG. 1.
The thyristor of FIG. 1 includes an anode node that is shorted through an n-type well tie (nwt) to the nwell, and a cathode node that is shorted through a p-type well tie (pwt) to the p-well. The thyristor of FIG. 1 is illustrated in cross-sectional view in FIG. 2, where the psd, and nsd notation indicate regions that can be formed using p-type and n-type source-drain formation processes respectively. Likewise, the n-well and p-well notations indicator regions that can be formed using well formation processes, while the pgc region is a doped region known to be used in various processes including Bipolar-Complimentary Oxide Semiconductor (BiCMOS) processes. The thyristor of FIG. 2 requires a voltage and trigger current large enough to protect against latch-up of the thyrister during normal operation, while still maintaining a trigger voltage sufficiently low to activate and clamp during an ESD event. However, the trigger voltage of the prior art thyrister of FIGS. 1 and 2 can result in too large a voltage drop when used in voltage sensitive applications, such as for providing ESD protection between in ground nodes.
Another technique to protect against ESD damage of semiconductor devices is to connect otherwise isolated ground references to each other using opposing p-n junction diodes in parallel. While this allows for ESD current to flow from one ground reference node to another, it does so at the cost of introducing the diode junction capacitance between the two ground references, resulting in a reduced signal isolation between the grounds. The conventional thyristor of FIG. 1 if used to provide ESD protection between isolated ground nodes causes reduced signal isolation due to a relatively large associated capacitance of approximately 300 femptofarads, and has a trigger voltage which has been found to be too large to be an effective protection circuit against damage caused by ESD events. It should be apparent from the above discussion that a thyristor device capable of providing high conductance protection during ESD events and a high degree of signal isolation along with a low capacitance during normal operation would be useful.